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I've got the whole thing pretty much coded up. It simulates fine (using ModelSim). I put test signals in and out of it, it decodes them to parallel, good to go.
The only real worry I have is whether or not this thing is likely to actually synthesize and function when I put it onto the FPGA (Xilinx Virtex-4). My biggest concern is that my clock will be off no matter what I do; the FPGA runs on a 100MHz clock, and there's no way to divide that down to come out evenly to any common serial baudrate (I've gone with 9600).
Right now I'm clocking it using a basic counter, that oscillates every 5207 clock cycles, or basically about 6ns fast per cycle. Like I said, it simulates fine (I ran it through like 30 cycles...anything more starts to take forever) but obviously in the "real world" it's going to be running through a hell of a lot more cycles than that, and that 6ns will eventually add up.
I'm thinking this will be particularly problematic when talking about receiving...transmitting should still work out okay.
Anyway, the FPGA only offers TX, RX, and ground connections. None of the other 6 pins are functional. Has anybody had any luck getting bi-directional serial communications over RS-232 with such a setup?
Anyway, in case any more details would help I'm implementing this using a simple state machine; two, actually...one for receiving and one for sending. The receiving state machine sits idle for as long as RX is high, then on the falling edge of RX moves through 10 states: one to check the start bit, 8 to place the next 8 bits into an 8-bit register bit by bit, and one last that checks the stop bit, outputs the register, etc.
tl;dr: Is there any chance this will actually work? Yes, this means you have to go back and read it. Like I said, I think timing is the issue I'm most worried about here.