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VHDL counter problem
Xego
Registered User regular
Registered User regular
It's final projects time again and my computer logic design class gave our group what I thought to be a pretty simple project, an up.down 0 to 9999 counter with reset and pause in VHDL. We designed the display, reset, and pause with no difficulties whatsoever, but the counter is giving us some unforeseen trouble.
The plan for the counter was to make a state machine that starts out at a state 0 and every clock cycle changes to either the next state or previous state depending on if our "up" switch is flipped or not. Then what we wanted it to do was to have an output send out a 1 when going from state 9 back to state 0 and also when going from state 0 to state 9. This output would be fed into the clock input for the next digit so that the next digit would only change state when the previous digit changed to and from those specific states. The problem we've run into is that the next digit does indeed count up or down on time, but it does it twice... So when what we end up seeing is something like this.
0008
0009
0010
0011
0022
0023
0024
We have no idea why it would change state twice like that, and it even waits a little bit before doing it so, if counting up, it changes at 2 and, if counting down, at 7.
We just learned about the idea of a ripple counter in our last lecture so we had no knowledge of this idea before designing our counter and we don't know if this is a normal thing you have to take into account or if we're just wrong from a design standpoint. Does anyone have any advice or help about this kind of project?
The plan for the counter was to make a state machine that starts out at a state 0 and every clock cycle changes to either the next state or previous state depending on if our "up" switch is flipped or not. Then what we wanted it to do was to have an output send out a 1 when going from state 9 back to state 0 and also when going from state 0 to state 9. This output would be fed into the clock input for the next digit so that the next digit would only change state when the previous digit changed to and from those specific states. The problem we've run into is that the next digit does indeed count up or down on time, but it does it twice... So when what we end up seeing is something like this.
0008
0009
0010
0011
0022
0023
0024
We have no idea why it would change state twice like that, and it even waits a little bit before doing it so, if counting up, it changes at 2 and, if counting down, at 7.
We just learned about the idea of a ripple counter in our last lecture so we had no knowledge of this idea before designing our counter and we don't know if this is a normal thing you have to take into account or if we're just wrong from a design standpoint. Does anyone have any advice or help about this kind of project?
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Posts
If this occurs in simulation, then yeah, check what Phyphor said - you have a logic bug somewhere.
If this occurs on a board (and only on a board), check your timing analysis outputs for warnings - you may have chained too many combinational circuits together. If you're not comfortable doing timing analysis (e.g. Altera's TimeQuest, Xilinx's Trace), try and slow your system clock down - if the behaviour goes away, then you've got signal propagation issues like Phyphor said.
In fact, now that I type this out, I see that you win this round, Phyphor. =P